38 pts XtremeSystems

Think stage 2 looks a little buggy, maybe it's just me...

i think stage 2 should only be ddr2.

yeah in the whole competition is ddr2 completely useless becaus of ddr3 is best in all stages except the first one...

next time maybe this way:

stage 1: sdr

stage 2: ddr1

stage 3: ddr2

stage 4: ddr3

stage 5: so-dimm

Nah, should have included CAS 1 and CAS 3 and removed CAS 10.

Guys from HWBOT staff, could you take a look at my score and the comments, please.

Definitely it's not CL4, but it's the same for other boards, we can't tell all of them. You should take a decision about this stage. There might be problems with detection in other stages as well.

I already sent a PM regarding stage 2 to Massman three days ago, but I'll repost it in public.

I had a hard time believing all the CL4 scores that have been posted, so I checked some datasheets from both Elpida and Micron:

Micron D9GTR Datasheet, page 111:

CAS Latency (CL):

The CL is defined by MR0[6:4], as shown in Figure 53 on page 109. CAS latency is the

delay, in clock cycles, between the internal READ command and the availability of the

first bit of output data. The CL can be set to 5, 6, 7, 8, 9, or 10. DDR3 SDRAM do not

support half-clock latencies.

Also, right at the beginning it says:

• CAS (READ) latency (CL): 5, 6, 7, 8, 9, 10, or 11

• POSTED CAS ADDITIVE latency (AL): 0, CL - 1, CL - 2

• CAS (WRITE) latency (CWL): 5, 6, 7, 8, based on tCK

Then I checked Elpida's datasheets, I think the correct MGH-E datasheet is not available, so I had a look at the one for EDJ1108BASE in general. Right at the beginning it says:

• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11

• /CAS Write Latency (CWL): 5, 6, 7, 8

Seems like CL4 is not supported by DDR3 at all and the boards are running at some other CAS Latency. I know some guys think those clocks are real, but please show me CL5 at those clocks, it should be easy, right?

I heard some guys are also hoping for CL2 on DDR2, here's an excerpt from a Micron DDR2 datasheet:

CAS Latency (CL):

The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 36 (page 79). CL is

the delay, in clock cycles, between the registration of a READ command and the availability

of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, depending

on the speed grade option being used.

DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be

used as an unknown operation otherwise incompatibility with future versions may result.

So basically what you're saying is

CAS 2 = DDR

CAS 4 = DDR2

CAS 6,8,10 = DDR3

Yes.

Sounds reasonable - DDR2 for CL4:)

Excellent. I concur.

Yes, completely agree . Well, someone could participate with DDR2@CL6, so they should be allowed.

CL2 - DDR

CL4 - DDR2

CL6 - DDR2 & DDR3

CL8, CL10 - DDR3

PS: Moving results here, 'cause I have a feeling Massman will delete DDR3 submissions soon

Ok, here's the real deal. It seems that the board sets it to CL8 or CL7 at best.

Can't boot at 5-8-8-24 on same settings. Results speak for themselves.

There are other possible variants, but I lost enough time to test these 5. Don't mind Everest scores, we all know they are not consistent between runs, so it's there only to display detected timings.

 

Pi32M

 

6-6-6 => 16m 20.337s http://i.imgur.com/ktfFl.jpg

4-6-6 => 16m 29.791s http://i.imgur.com/ej94m.jpg

6-8-8 => 16m 29.963s http://i.imgur.com/Losu5.jpg

4-8-8 => 16m 44.735s http://i.imgur.com/NdTA0.jpg

8-8-8 => 16m 42.223s http://i.imgur.com/iHzfg.jpg

 

I've never stated it's a real CL4, but it's the same on other boards. This stage could be complete fiasco, because you can't test virtually every board with every possible bios version.

I already sent a PM regarding stage 2 to Massman three days ago, but I'll repost it in public.

I had a hard time believing all the CL4 scores that have been posted, so I checked some datasheets from both Elpida and Micron:

 

Micron D9GTR Datasheet, page 111:

CAS Latency (CL):

The CL is defined by MR0[6:4], as shown in Figure 53 on page 109. CAS latency is the

delay, in clock cycles, between the internal READ command and the availability of the

first bit of output data. The CL can be set to 5, 6, 7, 8, 9, or 10. DDR3 SDRAM do not

support half-clock latencies.

 

Also, right at the beginning it says:

• CAS (READ) latency (CL): 5, 6, 7, 8, 9, 10, or 11

• POSTED CAS ADDITIVE latency (AL): 0, CL - 1, CL - 2

• CAS (WRITE) latency (CWL): 5, 6, 7, 8, based on tCK

 

Then I checked Elpida's datasheets, I think the correct MGH-E datasheet is not available, so I had a look at the one for EDJ1108BASE in general. Right at the beginning it says:

• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11

• /CAS Write Latency (CWL): 5, 6, 7, 8

 

Seems like CL4 is not supported by DDR3 at all and the boards are running at some other CAS Latency. I know some guys think those clocks are real, but please show me CL5 at those clocks, it should be easy, right?

 

I heard some guys are also hoping for CL2 on DDR2, here's an excerpt from a Micron DDR2 datasheet:

CAS Latency (CL):

The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 36 (page 79). CL is

the delay, in clock cycles, between the registration of a READ command and the availability

of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, depending

on the speed grade option being used.

DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be

used as an unknown operation otherwise incompatibility with future versions may result.

I tried a run at settings equal to or close to my CAS 4 result with a CAS 5 setting as Don Dan had suggested. I have to agree, if it can do it at CAS 4 it should also work with a CAS 5 setting.

After trying it several times, it never booted with a CAS 5 setting at the tested speeds yet did with a CAS 4 setting.

With this testing I did on my own and with the results it showed I have to agree that CAS 4 should be left for DDR2, no DDR3 entries allowed for it and I have removed my DDR3 / CAS 4 submission from the comp.

Yeah it was nice to see that but if it's a flaw or bug of somekind it's not accurate and this needs to be addressed. I still have all the info for reposting that IF the staff here thinks it's OK but I don't believe that's gonna happen.

Most if not all DDR2 sticks will run with a CAS 6 setting and many DDR3 sticks will too as we know but DDR3 should easily mop the floor with DDR2 in the literal sense related to results.

in this thread i can feel the good old honest spirit of overclocking community.

So basically what you're saying is

 

CAS 2 = DDR

CAS 4 = DDR2

CAS 6,8,10 = DDR3

This is what I thought when I first saw the competition.

I think with my REX + D9GTR I am running CL5 @ 925MHz, not CL4. When I set CL5 in bios, I can still achieve 925MHz, but I ran maxxmem at CL4,5 & 6.

CL5 was always better than CL6. CL4 was always giving me the same scores (give or take normal deviation) as CL5.

I have deleted the submission.

Yea, make stage 2 DDR2 and let's go back to overclocking instead of seeing who can bug their result the best.

Yea, make stage 2 DDR2 and let's go back to overclocking instead of seeing who can bug their result the best.

I agree Pizzman. I would like to challenge you in DDR2 stage but unfortunately I sold my only GMH kit

in this thread i can feel the good old honest spirit of overclocking community.

so true bro!

So we are brushing this under the carpet too? I guess I will upload my score again...

DDR3 in CL4 stage is not valid and will be removed.

So, let's not try to bug as much scores as possible.

DDR3 in CL4 stage is not valid and will be removed.

 

So, let's not try to bug as much scores as possible.

All DDR3 Results from Stage 2 (CL4) have been blocked,

Please if there is new DDR3 results for this stage, report them and I will block them as ''Please use DDR2''

Good. Maybe you should add it to the list of limitations for the stage.

ah much better

thx @ massman and christian

Can you just disable uploading of DDR3 results in stage 2 and add it to the limitation rules?

thats a good idea. not everybody reads this thread before participating that competition...

Added limitation