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User Avatar imclaudiu's 13th Gen Intel Core i3-13100F at 4270.0 MHz with an Z790 UD Motherboard

2844 Marks

Hardware Details

Processor

AVX/AVX2 instructions Yes
AVX512 instructions No
Brand String 13th Gen Intel(R) Core(TM) i3-13100F
Family RaptorLake
Family RaptorLake
Feature Flags VMX, EIST, TM2, PCID, x2APIC, FPU, VME, PSE, MSR, PAE, MCE, APIC, MTRR, PAT, PSE-36, ACPI, SS, HTT, TM
Hybrid Core Architecture No
Instructions TSC, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AESNI, AVX
Intel® Speed Shift True
Intel® Turbo Boost Max True
Logical CPU P-Cores 8
Microcode Update 0x26
Model S
Physical CPU P-Cores 4
Possible Turbo Bins 0
Turbo Overclockable False
Undervolt Protection Yes

Operating System

Manufacturer Microsoft Corporation
Name Microsoft Windows 10 Pro
Version 10.0.19044

Motherboard

Manufacturer Gigabyte Technology Co., Ltd.
Model Z790 UD
Version x.x

Memory

Total Installed Memory 32.00 GB
Default Speed 6000 MT/s
Capacity 16.00 GB
Device Locator Controller0-ChannelA-DIMM1
Bank Label BANK 0
Manufacturer Kingston
Default Speed 6000 MT/s
Manufacturer Kingston
Capacity 16.00 GB
Device Locator Controller1-ChannelA-DIMM1
Bank Label BANK 0

Graphics

DAC Type Internal DAC(400MHz)
Driver Date 4/20/2023
Driver Version 31.0.14051.5006
Name AMD Radeon RX 6800 XT
RAM 4.00 GB

BIOS

Manufacturer American Megatrends International, LLC.
Release Date 10/11/2022
Version F2

BIOS/UEFI Settings

Processor

AVX2 Ratio Offset 0.0 x
Core Voltage 0.0 V
Core Voltage Offset 0.0 mV
Processor Core IccMax 511.75 A
Reference Clock 0.0 MHz

Processor Turbo Voltageoverride

Performance Core 0 Voltage Override 0.0 V
Performance Core 1 Voltage Override 0.0 V
Performance Core 2 Voltage Override 0.0 V
Performance Core 3 Voltage Override 0.0 V

Processor Turbo Voltageoffset

Performance Core 0 Voltage Offset 0.0 mV
Performance Core 1 Voltage Offset 0.0 mV
Performance Core 2 Voltage Offset 0.0 mV
Performance Core 3 Voltage Offset 0.0 mV

Processor Turbo Voltagemode

Performance Core 0 Voltage Mode Adaptive
Performance Core 1 Voltage Mode Adaptive
Performance Core 2 Voltage Mode Adaptive
Performance Core 3 Voltage Mode Adaptive

Processor Turbo Ratios

1 Active Performance Core 45.0 x
2 Active Performance Cores 45.0 x
3 Active Performance Cores 43.0 x
4 Active Performance Cores 43.0 x

Processor Turbo Ratiolimit

Performance Core 0 45.0 x
Performance Core 1 45.0 x
Performance Core 2 45.0 x
Performance Core 3 45.0 x

Processor Turbo

Processor Powercurrent

Turbo Boost Power Max 4095.875 W
Turbo Boost Power Time Window 8.0 Seconds
Turbo Boost Short Power Max 4095.875 W
Turbo Boost Short Power Max Enable Enable

Memory Xmp

CommandRate 0.0 n
CommandRate 0.0 n
CommandRate 0.0 n
CommandRate 0.0 n
CommandRate 0.0 n
CommandRate 0.0 n
CommandRate 0.0 n
CommandRate 0.0 n
CommandRate 0.0 n
CommandRate 0.0 n
Frequency 0.0 MHz
Frequency 3003.0 MHz
Frequency 0.0 MHz
Frequency 2801.0 MHz
Frequency 2403.0 MHz
Frequency 3003.0 MHz
Frequency 2403.0 MHz
Frequency 0.0 MHz
Frequency 2801.0 MHz
Frequency 0.0 MHz
MCVoltage 0.0 V
MCVoltage 0.0 V
MCVoltage 0.0 V
MCVoltage 0.0 V
MCVoltage 0.0 V
MCVoltage 0.0 V
MCVoltage 0.0 V
MCVoltage 1.3 V
MCVoltage 1.3 V
MCVoltage 0.0 V
VDD 1.25 V
VDD 0.0 V
VDD 1.35 V
VDD 1.35 V
VDD 0.0 V
VDD 0.0 V
VDD 0.0 V
VDD 1.1 V
VDD 1.1 V
VDD 1.25 V
VDDQ 1.1 V
VDDQ 0.0 V
VDDQ 0.0 V
VDDQ 1.1 V
VDDQ 1.25 V
VDDQ 0.0 V
VDDQ 0.0 V
VDDQ 1.35 V
VDDQ 1.35 V
VDDQ 1.25 V
VPP 1.8 V
VPP 1.8 V
VPP 1.8 V
VPP 0.0 V
VPP 1.8 V
VPP 1.8 V
VPP 0.0 V
VPP 0.0 V
VPP 1.8 V
VPP 0.0 V
tCCD_L 0.0 Cycles
tCCD_L 0.0 Cycles
tCCD_L 0.0 Cycles
tCCD_L 0.0 Cycles
tCCD_L 0.0 Cycles
tCCD_L 0.0 Cycles
tCCD_L 0.0 Cycles
tCCD_L 0.0 Cycles
tCCD_L 0.0 Cycles
tCCD_L 0.0 Cycles
tCCD_L_WR 0.0 Cycles
tCCD_L_WR 0.0 Cycles
tCCD_L_WR 0.0 Cycles
tCCD_L_WR 0.0 Cycles
tCCD_L_WR 0.0 Cycles
tCCD_L_WR 0.0 Cycles
tCCD_L_WR 0.0 Cycles
tCCD_L_WR 0.0 Cycles
tCCD_L_WR 0.0 Cycles
tCCD_L_WR 0.0 Cycles
tCCD_L_WR2 0.0 Cycles
tCCD_L_WR2 0.0 Cycles
tCCD_L_WR2 0.0 Cycles
tCCD_L_WR2 0.0 Cycles
tCCD_L_WR2 0.0 Cycles
tCCD_L_WR2 0.0 Cycles
tCCD_L_WR2 0.0 Cycles
tCCD_L_WR2 0.0 Cycles
tCCD_L_WR2 0.0 Cycles
tCCD_L_WR2 0.0 Cycles
tCCD_L_WTR 0.0 Cycles
tCCD_L_WTR 0.0 Cycles
tCCD_L_WTR 0.0 Cycles
tCCD_L_WTR 0.0 Cycles
tCCD_L_WTR 0.0 Cycles
tCCD_L_WTR 0.0 Cycles
tCCD_L_WTR 0.0 Cycles
tCCD_L_WTR 0.0 Cycles
tCCD_L_WTR 0.0 Cycles
tCCD_L_WTR 0.0 Cycles
tCCD_S_WTR 0.0 Cycles
tCCD_S_WTR 0.0 Cycles
tCCD_S_WTR 0.0 Cycles
tCCD_S_WTR 0.0 Cycles
tCCD_S_WTR 0.0 Cycles
tCCD_S_WTR 0.0 Cycles
tCCD_S_WTR 0.0 Cycles
tCCD_S_WTR 0.0 Cycles
tCCD_S_WTR 0.0 Cycles
tCCD_S_WTR 0.0 Cycles
tCL 0.0 Cycles
tCL 38.0 Cycles
tCL 0.0 Cycles
tCL 40.0 Cycles
tCL 32.0 Cycles
tCL 38.0 Cycles
tCL 32.0 Cycles
tCL 0.0 Cycles
tCL 0.0 Cycles
tCL 40.0 Cycles
tFAW 0.0 Cycles
tFAW 0.0 Cycles
tFAW 0.0 Cycles
tFAW 0.0 Cycles
tFAW 0.0 Cycles
tFAW 0.0 Cycles
tFAW 0.0 Cycles
tFAW 0.0 Cycles
tFAW 0.0 Cycles
tFAW 0.0 Cycles
tRAS 80.0 Cycles
tRAS 80.0 Cycles
tRAS 0.0 Cycles
tRAS 0.0 Cycles
tRAS 0.0 Cycles
tRAS 70.0 Cycles
tRAS 70.0 Cycles
tRAS 0.0 Cycles
tRAS 80.0 Cycles
tRAS 80.0 Cycles
tRC 0.0 Cycles
tRC 135.0 Cycles
tRC 116.0 Cycles
tRC 118.0 Cycles
tRC 118.0 Cycles
tRC 135.0 Cycles
tRC 0.0 Cycles
tRC 116.0 Cycles
tRC 0.0 Cycles
tRC 0.0 Cycles
tRCD 0.0 Cycles
tRCD 0.0 Cycles
tRCD 38.0 Cycles
tRCD 38.0 Cycles
tRCD 38.0 Cycles
tRCD 0.0 Cycles
tRCD 0.0 Cycles
tRCD 38.0 Cycles
tRCD 40.0 Cycles
tRCD 40.0 Cycles
tRFC1 0.0 Cycles
tRFC1 884.0 Cycles
tRFC1 884.0 Cycles
tRFC1 708.0 Cycles
tRFC1 824.0 Cycles
tRFC1 708.0 Cycles
tRFC1 0.0 Cycles
tRFC1 0.0 Cycles
tRFC1 0.0 Cycles
tRFC1 824.0 Cycles
tRFC2 384.0 Cycles
tRFC2 480.0 Cycles
tRFC2 447.0 Cycles
tRFC2 480.0 Cycles
tRFC2 447.0 Cycles
tRFC2 0.0 Cycles
tRFC2 0.0 Cycles
tRFC2 0.0 Cycles
tRFC2 0.0 Cycles
tRFC2 384.0 Cycles
tRFCsb 312.0 Cycles
tRFCsb 364.0 Cycles
tRFCsb 390.0 Cycles
tRFCsb 312.0 Cycles
tRFCsb 0.0 Cycles
tRFCsb 390.0 Cycles
tRFCsb 364.0 Cycles
tRFCsb 0.0 Cycles
tRFCsb 0.0 Cycles
tRFCsb 0.0 Cycles
tRP 38.0 Cycles
tRP 38.0 Cycles
tRP 0.0 Cycles
tRP 0.0 Cycles
tRP 0.0 Cycles
tRP 40.0 Cycles
tRP 40.0 Cycles
tRP 38.0 Cycles
tRP 38.0 Cycles
tRP 0.0 Cycles
tRRD_L 0.0 Cycles
tRRD_L 0.0 Cycles
tRRD_L 0.0 Cycles
tRRD_L 0.0 Cycles
tRRD_L 0.0 Cycles
tRRD_L 0.0 Cycles
tRRD_L 0.0 Cycles
tRRD_L 0.0 Cycles
tRRD_L 0.0 Cycles
tRRD_L 0.0 Cycles
tRTP 0.0 Cycles
tRTP 0.0 Cycles
tRTP 0.0 Cycles
tRTP 0.0 Cycles
tRTP 0.0 Cycles
tRTP 0.0 Cycles
tRTP 0.0 Cycles
tRTP 0.0 Cycles
tRTP 0.0 Cycles
tRTP 0.0 Cycles
tWR 0.0 Cycles
tWR 0.0 Cycles
tWR 72.0 Cycles
tWR 84.0 Cycles
tWR 0.0 Cycles
tWR 72.0 Cycles
tWR 84.0 Cycles
tWR 0.0 Cycles
tWR 90.0 Cycles
tWR 90.0 Cycles

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