|
|
1183 MHz
|
4x ARM Cortex-A7
|
ARMv7-A (32bit RISC)
|
10
SUBS
|
|
|
1200 MHz
|
4x ARM Cortex-A7
|
ARMv7-A (32bit RISC)
|
2
SUBS
|
|
|
1200 MHz
|
4x Cortex-A53 (Mediatek)
|
ARMv8 (A32, A64) (64bit RISC)
|
60
SUBS
|
|
|
1200 MHz
|
4x ARM Cortex-A7
|
ARMv7-A (32bit RISC)
|
1
SUBS
|
|
|
1000 MHz
|
1x Marvell Sheeva
|
ARMv5 (32bit RISC)
|
1
SUBS
|
|
|
1200 MHz
|
3x Marvell ARMv7 MPcore
|
ARMv7 (32bit RISC)
|
|
|
|
1200 MHz
|
4x ARM Cortex-A7
|
ARMv7-A (32bit RISC)
|
87
SUBS
|
|
|
800 MHz
|
1x Marvell Sheeva
|
ARMv5 (32bit RISC)
|
|
|
|
1200 MHz
|
4x ARM Cortex-A7
|
ARMv7-A (32bit RISC)
|
|
|
|
1300 MHz
|
4x ARM Cortex-A7
|
ARMv7-A (32bit RISC)
|
|
|
|
624 MHz
|
1x Intel XScale
|
ARM (32bit RISC)
|
|
|
|
624 MHz
|
1x Intel XScale
|
ARM (32bit RISC)
|
|
|
|
806 MHz
|
1x Intel XScale
|
ARM (32bit RISC)
|
1
SUBS
|
|
|
624 MHz
|
1x Intel XScale
|
ARM (32bit RISC)
|
|
|
|
624 MHz
|
1x Marvell Sheeva
|
ARMv5 (32bit RISC)
|
|
|
|
800 MHz
|
1x Marvell Sheeva
|
ARMv5 (32bit RISC)
|
|
|
|
1000 MHz
|
1x Marvell Sheeva
|
ARMv5 (32bit RISC)
|
|
|
|
624 MHz
|
1x Marvell Sheeva
|
ARMv5 (32bit RISC)
|
|
|
|
806 MHz
|
1x Marvell Sheeva
|
ARMv5 (32bit RISC)
|
|
|
|
1000 MHz
|
1x Marvell Sheeva
|
ARMv5 (32bit RISC)
|
|
|
|
800 MHz
|
1x Marvell Sheeva
|
ARMv5 (32bit RISC)
|
|
|
|
624 MHz
|
1x Marvell Sheeva
|
ARMv5 (32bit RISC)
|
|
|
|
|
1x Marvell Sheeva
|
ARMv5 (32bit RISC)
|
|
|
|
624 MHz
|
1x Marvell Sheeva
|
ARMv5 (32bit RISC)
|
|
|
|
800 MHz
|
1x Marvell Sheeva
|
ARMv5 (32bit RISC)
|
|
|
|
1200 MHz
|
2x ARM Cortex-A9
|
ARMv7 (32bit RISC)
|
165
SUBS
|
|
|
1205 MHz
|
2x ARM Cortex-A9
|
ARMv7 (32bit RISC)
|
125
SUBS
|
|
|
1200 MHz
|
2x ARM Cortex-A9
|
ARMv7 (32bit RISC)
|
|
|
|
520 MHz
|
1x Intel XScale
|
ARM (32bit RISC)
|
|