UMC
| Model | Clock | Cores | Architecture | Submissions |
|---|---|---|---|---|
| 25 MHz | 1x U5S | x86 (32bit CISC) | ||
| 33 MHz | 1x U5S | x86 (32bit CISC) | ||
| 33 MHz | 1x U5S | x86 (32bit CISC) | ||
| 40 MHz | 1x U5S | x86 (32bit CISC) | ||
| 40 MHz | 1x U5S | x86 (32bit CISC) |
Official HWBOT Partner
| Model | Clock | Cores | Architecture | Submissions |
|---|---|---|---|---|
| 25 MHz | 1x U5S | x86 (32bit CISC) | ||
| 33 MHz | 1x U5S | x86 (32bit CISC) | ||
| 33 MHz | 1x U5S | x86 (32bit CISC) | ||
| 40 MHz | 1x U5S | x86 (32bit CISC) | ||
| 40 MHz | 1x U5S | x86 (32bit CISC) |
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