|
|
|
1x Cortex-A5
|
ARMv7 (32bit RISC)
|
2
SUBS
|
|
|
1000 MHz
|
1x Cortex-A5
|
ARMv7 (32bit RISC)
|
76
SUBS
|
|
|
600 MHz
|
1x Cortex-A5
|
ARMv7 (32bit RISC)
|
16
SUBS
|
|
|
800 MHz
|
1x Cortex-A5
|
ARMv7 (32bit RISC)
|
146
SUBS
|
|
|
600 MHz
|
1x Cortex-A5
|
ARMv7 (32bit RISC)
|
1
SUBS
|
|
|
800 MHz
|
1x Cortex-A5
|
ARMv7 (32bit RISC)
|
8
SUBS
|
|
|
1000 MHz
|
1x Cortex-A5
|
ARMv7 (32bit RISC)
|
173
SUBS
|
|
|
1000 MHz
|
1x Cortex-A5
|
ARMv7 (32bit RISC)
|
|
|
|
800 MHz
|
1x Cortex-A5
|
ARMv7 (32bit RISC)
|
|
|
|
1008 MHz
|
1x Cortex-A5
|
ARMv7 (32bit RISC)
|
|
|
|
1000 MHz
|
1x Cortex-A5
|
ARMv7 (32bit RISC)
|
|
|
|
800 MHz
|
1x Cortex-A5
|
ARMv7 (32bit RISC)
|
|